1. Field of the Invention
The present invention relates to analog to digital converters (ADCs), and more specifically to a successive approximation (SAR) ADC operating with both high accuracy and (high) throughput performance.
2. Related Art
Analog to digital converters (ADCs) are used to generate a sequence of digital codes representing the respective signal levels of an analog signal as is well known in the relevant art. In general, an ADC receives a reference voltage also as input, with the voltage indicating the maximum input voltage level.
Assuming the ADC is to generate an N-bit digital code, a digital code ideally equals (Vin*2N/Vref), wherein Vref, Vin, * and / respectively represent the reference voltage, voltage level of a sample of the input signal, multiplication operator and division operator. In addition, a voltage level corresponding to one least significant bit (LSB) equals (Vref/2N).
ADCs often employ successive approximation principle (SAP) for such a conversion. ADCs implemented using SAP are generally referred to as SAR (successive approximation register) ADCs as a register is used to store the codes used to generate an intermediate analog signal.
In a typical SAP based implementation, each bit of a digital code (with the digital code representing a sample of the analog signal) is determined in a single iteration, starting from the most significant bit. To determine the most significant bit, the most significant bit is set to a specific logical value (e.g., 1) and the following bits to the other logical value (0), and the resulting number is converted to an intermediate analog signal (generally using a digital to analog converter (DAC), contained in the ADC).
Assuming the specific logical value equals 1, the value of the most significant bit of the digital code is determined to equal 0 if the sample of the analog signal has less voltage than the intermediate analog signal, or else to 1. The next significant bit may be set to 1 (while setting the most significant bit to the determined value) and the following bits to 0, and the resulting number is used to generate a new intermediate analog signal.
The new intermediate analog signal is compared with the sample of the analog signal to determine the corresponding (next significant) bit of the digital code. The approach is continued until all the bits of the digital code are determined. Other digital codes representing an analog signal may be generated at a desired sampling interval.
Speed of a SAR ADC is typically determined by the time duration to perform each iteration. The time duration depends on several factors. One of such factors is the time taken by a DAC to generate an intermediate analog signal corresponding to the digital code in each iteration. There is a general need to increase speeds (or throughput performance) of ADCs, and accordingly it may be desirable to reduce the time taken to generate an intermediate analog signal corresponding to a digital code.
One challenge presented in such reduction is that the load that needs to be driven by a reference voltage, changes as bits are resolved, and the reference voltage changes transiently due to the changing load. At least when SAR ADCs need to operate at a high throughput performance, only a small time window (duration) may be available to resolve additional bits, and the value of the digital code may deviate from the ideal value depending on the difference of the offered reference voltage from the ideal reference voltage while the bits are resolved.
The degree of change may be different as different bits are being resolved. At least in situations when the change exceeds a threshold voltage equaling the resolution (voltage level equaling one least significant bit value) of the ADC, the output may deviate from an accurate value, and is undesirable.
The problem may be compounded with respect to high resolution ADCs, since the threshold voltage is inversely proportional to the ADC resolution.
Another challenge presented in reduction of time to generate an intermediate analog signal, is that the components used in DAC may need certain time to settle to the voltage level of reference voltage. If the time duration is not enough for the components to settle, the signal level of the intermediate analog signal may not represent the digital code accurately in each iteration. Even in such a situation the output digital code of an ADC may deviate from an ideal (accurate) value.
One approach to ensuring accurate digital codes is to decrease the throughput performance (speed or number of codes generated per second) of operation of an ADC, such that additional time is available for the various voltage levels to settle. Unfortunately, it is often desired to provide high throughput performance. What is therefore required is a SAR ADC, which provides accurate digital codes at high throughput performance.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.